aide!!

J

jony

Guest
J'ai écrit ce code qui décrivent un bloc de cartographie signal de pi / 4 DQPSK.
mais l'adresse ROM n'augmente pas.
quelqu'un peut m'aider?

C'est le code:

IEEE bibliothèque;
ieee.std_logic_1164.all utilisation;
ieee.std_logic_arith.all utilisation;
ieee.std_logic_unsigned.all utilisation;
ieee.math_real.all utilisation;

entité est signal_mapping1
port (horloge: dans std_logic;
Reset: en std_logic;
Activer: en std_logic;
in_I: en std_logic;
in_Q: en std_logic;

out_I: le Real;
out_Q: le Real
);
signal_mapping1 fin;

-------------------------------------------------- ------------

Behav architecture de signal_mapping1 estROM_Array type est un tableau (0 à 15)
du réel;

constante du contenu: ROM_Array: = (
0 => 1,0, - Supposons ROM a
1 => 0,0, - préenregistré valeur
2 => 0.70710_67811_86547_52440, - comme ce tableau
3 => 0.70710_67811_86547_52440, -
4 => 0,0, -
5 => 1,0, -
6 =>-0.70710_67811_86547_52440, -
7 => 0.70710_67811_86547_52440, -
8 => -1,0, -
9 => 0,0, -
10 =>-0.70710_67811_86547_52440, - 11 =>-0.70710_67811_86547_52440,
12 => 0,0, -
13 => -1,0, -
14 => 0.70710_67811_86547_52440,
15 =>-0.70710_67811_86547_52440,
Autres => 505,0 -
);
- Définir les états de la FSM modèle

address_i signal: integer: = 0;
address_q signal: integer: = 1;
commencer
processus (Horloge, Reset, in_q, in_i)

commencer

if (Reset = '1 ') puis
out_i <= contenu (0);
out_q <= contenu (1);

elsif (Clock'event et Horloge = '1 ') puis
si l'option Activer = '1 'alors

if (in_q = '0 'et in_i = '0'), puis
out_q <= contenu (address_q 2);
out_i <= contenu (address_i 2);
<= Address_i address_i 2;
address_q <= address_q 2;elsif (in_q = '1 'et in_i = '0'), puis
out_q <= contenu (address_q 4);
out_i <= contenu (address_i 4);
<= Address_i address_i 4;
address_q <= address_q 4;elsif (in_q = '0 'et in_i = '1') puis
out_q <= contenu (address_q 6);
out_i <= contenu (address_i 6);
<= Address_i address_i 6;
address_q <= address_q 6;elsif (in_q = '1 'et in_i = '0'), puis
out_q <= contenu (address_q

<img src="http://www.edaboard.com/images/smiles/icon_cool.gif" alt="Frais" border="0" />

;
out_i <= contenu (address_i

<img src="http://www.edaboard.com/images/smiles/icon_cool.gif" alt="Frais" border="0" />

;
<= Address_i address_i 8;
address_q <= address_q 8;
fin si;
d'autre
out_q <= 505,0;
<= 505,0 out_i;
fin si;

fin si;
processus de bout;
Behav fin;

-------------------------------------------------- ------------

 
Je pense que vous avez deux déclarations de elsif que les entrées et in_q in_i ont la même valeur (in_q = '1 ', in_i = '0'):

Code:elsif (in_q = '1 'et in_i = '0'), puis

out_q <= contenu (address_q 4);

out_i <= contenu (address_i 4);

<= Address_i address_i 4;

address_q <= address_q 4;elsif (in_q = '1 'et in_i = '0'), puis

out_q <= contenu (address_q Cool;

out_i <= contenu (address_i Cool;

<= Address_i address_i 8;

address_q <= address_q 8;

 
vous avez eu raison, mais encore il ne fonctionne pas
Voici le code correct et le banc d'essai
Code:IEEE bibliothèque;

ieee.std_logic_1164.all utilisation;

ieee.std_logic_arith.all utilisation;

ieee.std_logic_unsigned.all utilisation;

ieee.math_real.all utilisation;entité est signal_mapping1

port (horloge: dans std_logic;

Reset: en std_logic;

Activer: en std_logic;

in_I: en std_logic;

in_Q: en std_logic;out_I: le Real;

out_Q: le Real

);

signal_mapping1 fin;-------------------------------------------------- ------------Behav architecture de signal_mapping1 estROM_Array type est un tableau (0 à 15)

du réel;constante du contenu: ROM_Array: = (

0 => 1,0, - Supposons ROM a

1 => 0.0, - la valeur préenregistré

2 => 0.70710_67811_86547_52440, - comme ce tableau

3 => 0.70710_67811_86547_52440, -

4 => 0,0, -

5 => 1,0, -

6 =>-0.70710_67811_86547_52440, -

7 => 0.70710_67811_86547_52440, -

8 => -1,0, -

9 => 0,0, -

10 =>-0.70710_67811_86547_52440, -

11 =>-0.70710_67811_86547_52440, -

12 => 0,0, -

13 => -1,0, -

14 => 0.70710_67811_86547_52440,

15 =>-0.70710_67811_86547_52440,

Autres => 505,0 -

);address_i signal: integer: = 0;

address_q signal: integer: = 1;

commencer

processus (Horloge, Reset)

commencer

if (Reset = '1 ') puis

out_i <= contenu (0);

out_q <= contenu (1);

elsif (Clock'event et Horloge = '1 ') puis

si l'option Activer = '1 'alorsif (in_q = '0 'et in_i = '0'), puis

out_q <= contenu (address_q 2);

out_i <= contenu (address_i 2);

<= Address_i address_i 2;

address_q <= address_q 2;
elsif (in_q = '1 'et in_i = '0'), puis

out_q <= contenu (address_q 4);

out_i <= contenu (address_i 4);

<= Address_i address_i 4;

address_q <= address_q 4;elsif (in_q = '0 'et in_i = '1') puis

out_q <= contenu (address_q 6);

out_i <= contenu (address_i 6);

<= Address_i address_i 6;

address_q <= address_q 6;elsif (in_q = '1 'et in_i = '1') puis

out_q <= contenu (address_q 8);

out_i <= contenu (address_i 8);

<= Address_i address_i 8;

address_q <= address_q 8;

fin si;

d'autre

out_q <= 505,0;

<= 505,0 out_i;

fin si;fin si;

processus de bout;

Behav fin;-------------------------------------------------- ------------ ------------------- tbIEEE bibliothèque;

ieee.std_logic_1164.all utilisation;

signal_mapping_tb entité est

signal_mapping_tb fin;

signal_mapping_tb_arc architecture de signal_mapping_tb estcomposante est signal_mapping1

port (horloge: dans std_logic;

Reset: en std_logic;

Activer: en std_logic;

in_I: en std_logic;

in_Q: en std_logic;

out_I: le Real;

out_Q: le Real

);composante fin;

signal enable_tb: std_logic;

signal clock_tb: std_logic: = '1 ';

signal reset_tb: std_logic;

signal in_i_tb: std_logic;

signal in_q_tb: std_logic;

signal out_i_tb: real;

signal out_q_tb: real;clk_time constante: le temps: = 50 ns;

commencerUET: signal_mapping1

Plan du port (

enable => enable_tb,

CLOCK => clock_tb,

reset => reset_tb,

in_i => in_i_tb,

in_q => in_q_tb,

out_i => out_i_tb,

out_q => out_q_tb

);

clock_proc: Le processus

commencer

<Clock_tb = non (clock_tb);

attendre clk_time;

processus de bout clock_proc;

reset_in: PROCESSUS

BEGIN

<Reset_tb = '1 ';

Attendez 10 ns;

<Reset_tb = '0 ';

Attendre;

Terminer le processus reset_in;

enable_in: PROCESSUS

BEGIN

<Enable_tb = '1 ';

Attendez 10 ns;

<Enable_tb = '0 ';

Attendre;

Terminer le processus enable_in;<In_q_tb = '0 ', '1' après 200 ns, '0 'au bout de 400 ns, '1' après 600 ns

, '1 'Après 800 ns, '0' après 1000 ns, '1 'après 1200 ns, '0' après 1400 ns, '1 'après 1600 ns

, '1 'Après 1800 ns, '0' après 2000 ns;

<In_i_tb = '0 ', '1' après 200 ns, '0 'au bout de 400 ns, '1' après 600 ns

, '0 'Après 800 ns, '1' après 1000 ns, '1 'après 1200 ns, '0' après 1400 ns, '1 'après 1600 ns

, '0 'Après 1800 ns, '1' après 2000 ns;signal_mapping_tb_arc fin;

 
Code:enable_in: PROCESSUS

BEGIN

<Enable_tb = '1 ';

Attendez 10 ns;

<Enable_tb = '0 ';

Attendre;

Terminer le processus enable_in;

 
u Merci mais maintenant j'ai un nouveau problème.
Comment puis-je rendre l'augmentation de l'adresse ROM en mode circulaire?
address4 14 = adresse 2

 
Pour le mode circulaire, votre code doit être modifié comme suit:

Code:if (in_q = '0 'et in_i = '0'), puis

if (address_i = 14 et address_q = 15) puis

<Address_i = 0;

address_q <= 1;

out_q <= contenu (address_q);

out_i <= contenu (address_i);d'autre

out_q <= contenu (address_q 2);

out_i <= contenu (address_i 2);

<= Address_i address_i 2;

address_q <= address_q 2;

fin si;elsif (in_q = '1 'et in_i = '0'), puisif (address_i> = 12 et address_q> = 13) puisout_q <= contenu (address_q - 12);

<= Out_i contenu (address_i - 12);

<= Address_i address_i - 12;

address_q <= address_q - 12;d'autre

out_q <= contenu (address_q 4);

out_i <= contenu (address_i 4);

<= Address_i address_i 4;

address_q <= address_q 4;

fin si;elsif (in_q = '0 'et in_i = '1') puisif (address_i> = 10 et address_q> = 11) puisout_q <= contenu (address_q - 10);

<= Out_i contenu (address_i - 10);

<= Address_i address_i - 10;

address_q <= address_q - 10;

d'autre

out_q <= contenu (address_q 6);

out_i <= contenu (address_i 6);

<= Address_i address_i 6;

address_q <= address_q 6;

fin si;elsif (in_q = '1 'et in_i = '1') puisif (address_i> = 8 et address_q> = 9), puisout_q <= contenu (address_q - 8);

<= Out_i contenu (address_i - 8);

<= Address_i address_i - 8;

address_q <= address_q - 8;d'autreout_q <= contenu (address_q 8);

out_i <= contenu (address_i 8);

<= Address_i address_i 8;

address_q <= address_q 8;

fin si;
 
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