J
jaloux
Guest
J'ai un méga-fonction (clearbox), qui est généré par qu (at) 2 postes locaux v4.1 utilisant le plug-in MegaWizad manager, mais lorsque je présente une synthèse utilisant clearbox Synplify Pro v7.7, certaines erreurs se sont produites, comme "La référence au indéfini module carry_sum ".
fifo_33_32.v en pièce jointe est généré par la clearbox qu (at) RTU, C'est un synchronisée FIFO (synchroniser la lecture et l'écriture de "rdclk» et «wrclk ', respectivement, les horloges sont synchronisées et entier des multiples les uns des autres).
J'ai ajouté dans le altera_mf.v Synplify projet contenant fifo_33_32.v, qui est le @ ltera liberary pour megafunction.
Si vous avez besoin de plus d'informations, dites-le moi.
Merci d'avance.
BTW: messages d'erreur ci-dessous est généré par Synplify.@ E: CG106: fifo_33_32.v (3085): Reference to undefined module carry_sum @ E: "e: \ wyy \ trash \ syncfifo \ fifo_33_32.v": 3085:13:3085:20
@ E: CG106: fifo_33_32.v (3091): Reference to undefined module carry_sum @ E: "e: \ wyy \ trash \ syncfifo \ fifo_33_32.v": 3091:13:3091:20
@ E: CG106: fifo_33_32.v (3100): Reference to undefined module carry_sum @ E: "e: \ wyy \ trash \ syncfifo \ fifo_33_32.v": 3100:13:3100:20
@ E: CG106: fifo_33_32.v (3106): Reference to undefined module carry_sum @ E: "e: \ wyy \ trash \ syncfifo \ fifo_33_32.v": 3106:13:3106:20
@ E: CG106: fifo_33_32.v (3112): Reference to undefined module carry_sum @ E: "e: \ wyy \ trash \ syncfifo \ fifo_33_32.v": 3112:13:3112:20
@ E: CG106: fifo_33_32.v (3118): Reference to undefined module carry_sum @ E: "e: \ wyy \ trash \ syncfifo \ fifo_33_32.v": 3118:13:3118:20
@ E: CG106: fifo_33_32.v (3124): Reference to undefined module carry_sum @ E: "e: \ wyy \ trash \ syncfifo \ fifo_33_32.v": 3124:13:3124:20
@ E: CG106: fifo_33_32.v (3130): Reference to undefined module carry_sum @ E: "e: \ wyy \ trash \ syncfifo \ fifo_33_32.v": 3130:13:3130:20
@ E: CG106: fifo_33_32.v (3139): Reference to undefined module carry_sum @ E: "e: \ wyy \ trash \ syncfifo \ fifo_33_32.v": 3139:13:3139:20
@ E: CG106: fifo_33_32.v (3145): Reference to undefined module carry_sum @ E: "e: \ wyy \ trash \ syncfifo \ fifo_33_32.v": 3145:13:3145:20
@ E: CG106: fifo_33_32.v (3151): Reference to undefined module carry_sum @ E: "e: \ wyy \ trash \ syncfifo \ fifo_33_32.v": 3151:13:3151:20
@ E: CG106: fifo_33_32.v (3157): Reference to undefined module carry_sum @ E: "e: \ wyy \ trash \ syncfifo \ fifo_33_32.v": 3157:13:3157:20
@ E: CG106: fifo_33_32.v (3163): Reference to undefined module carry_sum @ E: "e: \ wyy \ trash \ syncfifo \ fifo_33_32.v": 3163:13:3163:20
@ E: CG106: fifo_33_32.v (3169): Reference to undefined module carry_sum @ E: "e: \ wyy \ trash \ syncfifo \ fifo_33_32.v": 3169:13:3169:20
@ E: CG106: fifo_33_32.v (3178): Reference to undefined module carry_sum @ E: "e: \ wyy \ trash \ syncfifo \ fifo_33_32.v": 3178:13:3178:17
@ E: CG106: fifo_33_32.v (3184): Reference to undefined module carry_sum @ E: "e: \ wyy \ trash \ syncfifo \ fifo_33_32.v": 3184:13:3184:19
@ E: CG106: fifo_33_32.v (3190): Reference to undefined module carry_sum @ E: "e: \ wyy \ trash \ syncfifo \ fifo_33_32.v": 3190:13:3190:19
@ E: CG106: fifo_33_32.v (3196): Reference to undefined module carry_sum @ E: "e: \ wyy \ trash \ syncfifo \ fifo_33_32.v": 3196:13:3196:19
@ E: CG106: fifo_33_32.v (3202): Reference to undefined module carry_sum @ E: "e: \ wyy \ trash \ syncfifo \ fifo_33_32.v": 3202:13:3202:19
@ E: CG106: fifo_33_32.v (3208): Reference to undefined module carry_sum @ E: "e: \ wyy \ trash \ syncfifo \ fifo_33_32.v": 3208:13:3208:19
@ E: CG106: fifo_33_32.v (3214): Reference to undefined module carry_sum @ E: "e: \ wyy \ trash \ syncfifo \ fifo_33_32.v": 3214:13:3214:19
@ E: CS165: fifo_33_32.v (3180): Expecting fil de connexion de sortie @ E: "e: \ wyy \ trash \ syncfifo \ fifo_33_32.v": 3180:10:3180:39
@ E: CS165: fifo_33_32.v (3182): Expecting fils de connexion de sortie @ E: "e: \ wyy \ trash \ syncfifo \ fifo_33_32.v": 3182:10:3182:39
@ E: CL175: fifo_33_32.v (3052): Multiple non-conducteurs pour Tristate net wire_cs13a_sin [5] en fifo_33_32_alt_sync_fifo_aem @ E: "e: \ wyy \ trash \ syncfifo \ fifo_33_32.v": 3052:15:3052:29
24 Verilog Compiler les erreurs
fifo_33_32.v en pièce jointe est généré par la clearbox qu (at) RTU, C'est un synchronisée FIFO (synchroniser la lecture et l'écriture de "rdclk» et «wrclk ', respectivement, les horloges sont synchronisées et entier des multiples les uns des autres).
J'ai ajouté dans le altera_mf.v Synplify projet contenant fifo_33_32.v, qui est le @ ltera liberary pour megafunction.
Si vous avez besoin de plus d'informations, dites-le moi.
Merci d'avance.
BTW: messages d'erreur ci-dessous est généré par Synplify.@ E: CG106: fifo_33_32.v (3085): Reference to undefined module carry_sum @ E: "e: \ wyy \ trash \ syncfifo \ fifo_33_32.v": 3085:13:3085:20
@ E: CG106: fifo_33_32.v (3091): Reference to undefined module carry_sum @ E: "e: \ wyy \ trash \ syncfifo \ fifo_33_32.v": 3091:13:3091:20
@ E: CG106: fifo_33_32.v (3100): Reference to undefined module carry_sum @ E: "e: \ wyy \ trash \ syncfifo \ fifo_33_32.v": 3100:13:3100:20
@ E: CG106: fifo_33_32.v (3106): Reference to undefined module carry_sum @ E: "e: \ wyy \ trash \ syncfifo \ fifo_33_32.v": 3106:13:3106:20
@ E: CG106: fifo_33_32.v (3112): Reference to undefined module carry_sum @ E: "e: \ wyy \ trash \ syncfifo \ fifo_33_32.v": 3112:13:3112:20
@ E: CG106: fifo_33_32.v (3118): Reference to undefined module carry_sum @ E: "e: \ wyy \ trash \ syncfifo \ fifo_33_32.v": 3118:13:3118:20
@ E: CG106: fifo_33_32.v (3124): Reference to undefined module carry_sum @ E: "e: \ wyy \ trash \ syncfifo \ fifo_33_32.v": 3124:13:3124:20
@ E: CG106: fifo_33_32.v (3130): Reference to undefined module carry_sum @ E: "e: \ wyy \ trash \ syncfifo \ fifo_33_32.v": 3130:13:3130:20
@ E: CG106: fifo_33_32.v (3139): Reference to undefined module carry_sum @ E: "e: \ wyy \ trash \ syncfifo \ fifo_33_32.v": 3139:13:3139:20
@ E: CG106: fifo_33_32.v (3145): Reference to undefined module carry_sum @ E: "e: \ wyy \ trash \ syncfifo \ fifo_33_32.v": 3145:13:3145:20
@ E: CG106: fifo_33_32.v (3151): Reference to undefined module carry_sum @ E: "e: \ wyy \ trash \ syncfifo \ fifo_33_32.v": 3151:13:3151:20
@ E: CG106: fifo_33_32.v (3157): Reference to undefined module carry_sum @ E: "e: \ wyy \ trash \ syncfifo \ fifo_33_32.v": 3157:13:3157:20
@ E: CG106: fifo_33_32.v (3163): Reference to undefined module carry_sum @ E: "e: \ wyy \ trash \ syncfifo \ fifo_33_32.v": 3163:13:3163:20
@ E: CG106: fifo_33_32.v (3169): Reference to undefined module carry_sum @ E: "e: \ wyy \ trash \ syncfifo \ fifo_33_32.v": 3169:13:3169:20
@ E: CG106: fifo_33_32.v (3178): Reference to undefined module carry_sum @ E: "e: \ wyy \ trash \ syncfifo \ fifo_33_32.v": 3178:13:3178:17
@ E: CG106: fifo_33_32.v (3184): Reference to undefined module carry_sum @ E: "e: \ wyy \ trash \ syncfifo \ fifo_33_32.v": 3184:13:3184:19
@ E: CG106: fifo_33_32.v (3190): Reference to undefined module carry_sum @ E: "e: \ wyy \ trash \ syncfifo \ fifo_33_32.v": 3190:13:3190:19
@ E: CG106: fifo_33_32.v (3196): Reference to undefined module carry_sum @ E: "e: \ wyy \ trash \ syncfifo \ fifo_33_32.v": 3196:13:3196:19
@ E: CG106: fifo_33_32.v (3202): Reference to undefined module carry_sum @ E: "e: \ wyy \ trash \ syncfifo \ fifo_33_32.v": 3202:13:3202:19
@ E: CG106: fifo_33_32.v (3208): Reference to undefined module carry_sum @ E: "e: \ wyy \ trash \ syncfifo \ fifo_33_32.v": 3208:13:3208:19
@ E: CG106: fifo_33_32.v (3214): Reference to undefined module carry_sum @ E: "e: \ wyy \ trash \ syncfifo \ fifo_33_32.v": 3214:13:3214:19
@ E: CS165: fifo_33_32.v (3180): Expecting fil de connexion de sortie @ E: "e: \ wyy \ trash \ syncfifo \ fifo_33_32.v": 3180:10:3180:39
@ E: CS165: fifo_33_32.v (3182): Expecting fils de connexion de sortie @ E: "e: \ wyy \ trash \ syncfifo \ fifo_33_32.v": 3182:10:3182:39
@ E: CL175: fifo_33_32.v (3052): Multiple non-conducteurs pour Tristate net wire_cs13a_sin [5] en fifo_33_32_alt_sync_fifo_aem @ E: "e: \ wyy \ trash \ syncfifo \ fifo_33_32.v": 3052:15:3052:29
24 Verilog Compiler les erreurs