multisources erreur lors de la synthèse

[karper1986]

Salut les amis,

J'ai cette erreur en faisant la synthèse et bloqués pendant environ une semaine.Si quelqu'un a une idée, s'il vous plaît Indiquez-moi ce que la correction devrait j'ai faite dans le code.

J'utilise Xilinx ISE 11,1

module AGU (
CLK,
en_fft,
readmem_en,
memwrite_en,
agu_rd_addr0,
agu_rd_addr1,
agu_rd_addr2,
agu_rd_addr3,
agu_rd_addr4,
agu_rd_addr5,
agu_rd_addr6,
agu_rd_addr7,
agu_wr_addr0,
agu_wr_addr1,
agu_wr_addr2,
agu_wr_addr3,
agu_wr_addr4,
agu_wr_addr5,
agu_wr_addr6,
agu_wr_addr7
);

entrée CLK;
readmem_en d'entrée;
memwrite_en d'entrée;
en_fft d'entrée;

sortie [2:0] agu_rd_addr0;
sortie [2:0] agu_rd_addr1;
sortie [2:0] agu_rd_addr2;
sortie [2:0] agu_rd_addr3;
sortie [2:0] agu_rd_addr4;
sortie [2:0] agu_rd_addr5;
sortie [2:0] agu_rd_addr6;
sortie [2:0] agu_rd_addr7;

sortie [2:0] agu_wr_addr0;
sortie [2:0] agu_wr_addr1;
sortie [2:0] agu_wr_addr2;
sortie [2:0] agu_wr_addr3;
sortie [2:0] agu_wr_addr4;
sortie [2:0] agu_wr_addr5;
sortie [2:0] agu_wr_addr6;
sortie [2:0] agu_wr_addr7;

reg [3:0] counter_read;
reg [3:0] counter_write;
reg [2:0] agu_read [7:0];
reg [2:0] agu_write [7:0];

always @ (CLK posedge)
commencer
if (en_fft)
commencer
counter_read = 4'b0000; ---------- ceux-ci pourraient être un problème
counter_write = 4'b0000;
fin
fin

always @ (CLK negedge)
commencer
if (readmem_en)
commencer
cas (counter_read)
4'h0: begin
agu_read [0] <= 3'h0;
agu_read [1] <= 3'h1;
agu_read [2] <= 3'h2;
agu_read [3] <= 3'h3;
agu_read [4] <= 3'h4;
agu_read [5] <= 3'h5;
agu_read [6] <= 3'h6;
agu_read [7] <= 3'h7;
fin

4'h1: begin
agu_read [0] <= 3'h7;
agu_read [1] <= 3'h0;
agu_read [2] <= 3'h1;
agu_read [3] <= 3'h2;
agu_read [4] <= 3'h3;
agu_read [5] <= 3'h4;
agu_read [6] <= 3'h5;
agu_read [7] <= 3'h6;
fin

4'h2: begin
agu_read [0] <= 3'h6;
agu_read [1] <= 3'h7;
agu_read [2] <= 3'h0;
agu_read [3] <= 3'h1;
agu_read [4] <= 3'h2;
agu_read [5] <= 3'h3;
agu_read [6] <= 3'h4;
agu_read [7] <= 3'h5;
fin

4'h3: begin
agu_read [0] <= 3'h5;
agu_read [1] <= 3'h6;
agu_read [2] <= 3'h7;
agu_read [3] <= 3'h0;
agu_read [4] <= 3'h1;
agu_read [5] <= 3'h2;
agu_read [6] <= 3'h3;
agu_read [7] <= 3'h4;
fin

4'h4: begin
agu_read [0] <= 3'h4;
agu_read [1] <= 3'h5;
agu_read [2] <= 3'h6;
agu_read [3] <= 3'h7;
agu_read [4] <= 3'h0;
agu_read [5] <= 3'h1;
agu_read [6] <= 3'h2;
agu_read [7] <= 3'h3;
fin

4'h5: begin
agu_read [0] <= 3'h3;
agu_read [1] <= 3'h4;
agu_read [2] <= 3'h5;
agu_read [3] <= 3'h6;
agu_read [4] <= 3'h7;
agu_read [5] <= 3'h0;
agu_read [6] <= 3'h1;
agu_read [7] <= 3'h2;
fin

4'h6: begin
agu_read [0] <= 3'h2;
agu_read [1] <= 3'h3;
agu_read [2] <= 3'h4;
agu_read [3] <= 3'h5;
agu_read [4] <= 3'h6;
agu_read [5] <= 3'h7;
agu_read [6] <= 3'h0;
agu_read [7] <= 3'h1;
fin

4'h7: begin
agu_read [0] <= 3'h1;
agu_read [1] <= 3'h2;
agu_read [2] <= 3'h3;
agu_read [3] <= 3'h4;
agu_read [4] <= 3'h5;
agu_read [5] <= 3'h6;
agu_read [6] <= 3'h7;
agu_read [7] <= 3'h0;
fin

4'h8: begin
agu_read [0] <= 3'h0;
agu_read [1] <= 3'h0;
agu_read [2] <= 3'h0;
agu_read [3] <= 3'h0;
agu_read [4] <= 3'h0;
agu_read [5] <= 3'h0;
agu_read [6] <= 3'h0;
agu_read [7] <= 3'h0;
fin

4'h9: begin
agu_read [0] <= 3'h1;
agu_read [1] <= 3'h1;
agu_read [2] <= 3'h1;
agu_read [3] <= 3'h1;
agu_read [4] <= 3'h1;
agu_read [5] <= 3'h1;
agu_read [6] <= 3'h1;
agu_read [7] <= 3'h1;
fin

4'ha: begin
agu_read [0] <= 3'h2;
agu_read [1] <= 3'h2;
agu_read [2] <= 3'h2;
agu_read [3] <= 3'h2;
agu_read [4] <= 3'h2;
agu_read [5] <= 3'h2;
agu_read [6] <= 3'h2;
agu_read [7] <= 3'h2;
fin

4'hb: begin
agu_read [0] <= 3'h3;
agu_read [1] <= 3'h3;
agu_read [2] <= 3'h3;
agu_read [3] <= 3'h3;
agu_read [4] <= 3'h3;
agu_read [5] <= 3'h3;
agu_read [6] <= 3'h3;
agu_read [7] <= 3'h3;
fin

4'hc: begin
agu_read [0] <= 3'h4;
agu_read [1] <= 3'h4;
agu_read [2] <= 3'h4;
agu_read [3] <= 3'h4;
agu_read [4] <= 3'h4;
agu_read [5] <= 3'h4;
agu_read [6] <= 3'h4;
agu_read [7] <= 3'h4;
fin

4'hd: begin
agu_read [0] <= 3'h5;
agu_read [1] <= 3'h5;
agu_read [2] <= 3'h5;
agu_read [3] <= 3'h5;
agu_read [4] <= 3'h5;
agu_read [5] <= 3'h5;
agu_read [6] <= 3'h5;
agu_read [7] <= 3'h5;
fin

4'he: begin
agu_read [0] <= 3'h6;
agu_read [1] <= 3'h6;
agu_read [2] <= 3'h6;
agu_read [3] <= 3'h6;
agu_read [4] <= 3'h6;
agu_read [5] <= 3'h6;
agu_read [6] <= 3'h6;
agu_read [7] <= 3'h6;
fin

4'hf: begin
agu_read [0] <= 3'h7;
agu_read [1] <= 3'h7;
agu_read [2] <= 3'h7;
agu_read [3] <= 3'h7;
agu_read [4] <= 3'h7;
agu_read [5] <= 3'h7;
agu_read [6] <= 3'h7;
agu_read [7] <= 3'h7;
fin
ENDCASE

counter_read <= counter_read 1; ----- ceux-ci pourraient être un problème
fin
fin

always @ (CLK negedge)
commencer
if (memwrite_en)
commencer
cas (counter_write)
4'h0: begin
agu_write [0] <= 3'h0;
agu_write [1] <= 3'h1;
agu_write [2] <= 3'h2;
agu_write [3] <= 3'h3;
agu_write [4] <= 3'h4;
agu_write [5] <= 3'h5;
agu_write [6] <= 3'h6;
agu_write [7] <= 3'h7;
fin

4'h1: begin
agu_write [0] <= 3'h7;
agu_write [1] <= 3'h0;
agu_write [2] <= 3'h1;
agu_write [3] <= 3'h2;
agu_write [4] <= 3'h3;
agu_write [5] <= 3'h4;
agu_write [6] <= 3'h5;
agu_write [7] <= 3'h6;
fin

4'h2: begin
agu_write [0] <= 3'h6;
agu_write [1] <= 3'h7;
agu_write [2] <= 3'h0;
agu_write [3] <= 3'h1;
agu_write [4] <= 3'h2;
agu_write [5] <= 3'h3;
agu_write [6] <= 3'h4;
agu_write [7] <= 3'h5;
fin

4'h3: begin
agu_write [0] <= 3'h5;
agu_write [1] <= 3'h6;
agu_write [2] <= 3'h7;
agu_write [3] <= 3'h0;
agu_write [4] <= 3'h1;
agu_write [5] <= 3'h2;
agu_write [6] <= 3'h3;
agu_write [7] <= 3'h4;
fin

4'h4: begin
agu_write [0] <= 3'h4;
agu_write [1] <= 3'h5;
agu_write [2] <= 3'h6;
agu_write [3] <= 3'h7;
agu_write [4] <= 3'h0;
agu_write [5] <= 3'h1;
agu_write [6] <= 3'h2;
agu_write [7] <= 3'h3;
fin

4'h5: begin
agu_write [0] <= 3'h3;
agu_write [1] <= 3'h4;
agu_write [2] <= 3'h5;
agu_write [3] <= 3'h6;
agu_write [4] <= 3'h7;
agu_write [5] <= 3'h0;
agu_write [6] <= 3'h1;
agu_write [7] <= 3'h2;
fin

4'h6: begin
agu_write [0] <= 3'h2;
agu_write [1] <= 3'h3;
agu_write [2] <= 3'h4;
agu_write [3] <= 3'h5;
agu_write [4] <= 3'h6;
agu_write [5] <= 3'h7;
agu_write [6] <= 3'h0;
agu_write [7] <= 3'h1;
fin

4'h7: begin
agu_write [0] <= 3'h1;
agu_write [1] <= 3'h2;
agu_write [2] <= 3'h3;
agu_write [3] <= 3'h4;
agu_write [4] <= 3'h5;
agu_write [5] <= 3'h6;
agu_write [6] <= 3'h7;
agu_write [7] <= 3'h0;
fin

4'h8: begin
agu_write [0] <= 3'h0;
agu_write [1] <= 3'h0;
agu_write [2] <= 3'h0;
agu_write [3] <= 3'h0;
agu_write [4] <= 3'h0;
agu_write [5] <= 3'h0;
agu_write [6] <= 3'h0;
agu_write [7] <= 3'h0;
fin

4'h9: begin
agu_write [0] <= 3'h1;
agu_write [1] <= 3'h1;
agu_write [2] <= 3'h1;
agu_write [3] <= 3'h1;
agu_write [4] <= 3'h1;
agu_write [5] <= 3'h1;
agu_write [6] <= 3'h1;
agu_write [7] <= 3'h1;
fin

4'ha: begin
agu_write [0] <= 3'h2;
agu_write [1] <= 3'h2;
agu_write [2] <= 3'h2;
agu_write [3] <= 3'h2;
agu_write [4] <= 3'h2;
agu_write [5] <= 3'h2;
agu_write [6] <= 3'h2;
agu_write [7] <= 3'h2;
fin

4'hb: begin
agu_write [0] <= 3'h3;
agu_write [1] <= 3'h3;
agu_write [2] <= 3'h3;
agu_write [3] <= 3'h3;
agu_write [4] <= 3'h3;
agu_write [5] <= 3'h3;
agu_write [6] <= 3'h3;
agu_write [7] <= 3'h3;
fin

4'hc: begin
agu_write [0] <= 3'h4;
agu_write [1] <= 3'h4;
agu_write [2] <= 3'h4;
agu_write [3] <= 3'h4;
agu_write [4] <= 3'h4;
agu_write [5] <= 3'h4;
agu_write [6] <= 3'h4;
agu_write [7] <= 3'h4;
fin

4'hd: begin
agu_write [0] <= 3'h5;
agu_write [1] <= 3'h5;
agu_write [2] <= 3'h5;
agu_write [3] <= 3'h5;
agu_write [4] <= 3'h5;
agu_write [5] <= 3'h5;
agu_write [6] <= 3'h5;
agu_write [7] <= 3'h5;
fin

4'he: begin
agu_write [0] <= 3'h6;
agu_write [1] <= 3'h6;
agu_write [2] <= 3'h6;
agu_write [3] <= 3'h6;
agu_write [4] <= 3'h6;
agu_write [5] <= 3'h6;
agu_write [6] <= 3'h6;
agu_write [7] <= 3'h6;
fin

4'hf: begin
agu_write [0] <= 3'h7;
agu_write [1] <= 3'h7;
agu_write [2] <= 3'h7;
agu_write [3] <= 3'h7;
agu_write [4] <= 3'h7;
agu_write [5] <= 3'h7;
agu_write [6] <= 3'h7;
agu_write [7] <= 3'h7;
fin
ENDCASE

counter_write <= counter_write 1; ------------ ceux-ci pourraient être un problème
fin
fin

assigner agu_rd_addr0 = agu_read [0];
assigner agu_rd_addr1 = agu_read [1];
assigner agu_rd_addr2 = agu_read [2];
assigner agu_rd_addr3 = agu_read [3];
assigner agu_rd_addr4 = agu_read [4];
assigner agu_rd_addr5 = agu_read [5];
assigner agu_rd_addr6 = agu_read [6];
assigner agu_rd_addr7 = agu_read [7];

assigner agu_wr_addr0 = agu_write [0];
assigner agu_wr_addr1 = agu_write [1];
assigner agu_wr_addr2 = agu_write [2];
assigner agu_wr_addr3 = agu_write [3];
assigner agu_wr_addr4 = agu_write [4];
assigner agu_wr_addr5 = agu_write [5];
assigner agu_wr_addr6 = agu_write [6];
assigner agu_wr_addr7 = agu_write [7];endmoduleS'il vous plaît, donnez-moi quelques idées.

 

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[Tan]

Salut,
Multi Source de l'erreur se produit lorsque vous forcez un signal simultanément dans les deux processus.
Comme le processus se déroule en parallèle, le signal ne soit confondu la valeur à prendre.
par ex:

Process ()
commencer
a <= 5;
Terminer le processus;

seconde: process ()
commencer
a <= 6;
.......
......
.....
Terminer le processus;

ici le signe d'une montre multi source d'erreur car ces deux processus s'exécute en parallèle et "a" est confuse à laquelle la valeur à prendre.

J'espère que je suis clair.

 

[karper1986]

Merci Tan, vous avez très m'ont aidé.