tu peux m'aider pour faire le test benche de ce code la (test module)

[bouaoun]

-- Company:
-- Engineer:
--
-- Create Date:    11:23:33 06/03/2011
-- Design Name:
-- Module Name:    TEST - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity TEST is
port(A:inout std_logic_vector (7 downto 0 );
D: std_logic_vector (7 downto 0);
led0,led1,led2,led3,led4,led5,led6,led7ut std_logic_vector (7 downto 0 ));
end TEST;

architecture Behavioral of TEST is
signal y:std_logic_vector (7 downto 0 );
--signal D:std_logic_vector (7 downto 0 );

begin

process(A,D)

begin
--D <="11111111";
y <= '0' & A(7 downto 1);

--y<= A and D;
      if (y/="11111110" ) then
led0 <= "00000000";
else
led0<= "11111111";
end if;
y <= "00" & A(7 downto 2);


if (y /="11111100") then
led1 <= "00000000";
else
led1<= "11111111";
end if;
y <= "000" & A(7 downto 3);
if (y/="11111000" ) then
led2 <= "00000000";
else
led2<= "11111111";
end if;
y <= "0000" & A(7 downto 4);
if (y /="11110000") then
led3 <= "00000000";
else
led3<= "11111111";
end if;
y <= "00000" & A(7 downto 5);
if (y/="11100000") then
led4 <= "00000000";
else
led4<= "11111111";
end if;
y <= "000000" & A(7 downto 6);
if (y /="11000000") then
led5 <= "00000000";
else
led5<= "11111111";
end if;
y <= "0000000" & A(7 downto 7);
if (y/="10000000") then
led6 <= "00000000";
else
led6<= "11111111";
end if;
y <= "00000000" & A(7 downto 8);
if (y/="00000000") then
led7 <= "00000000";
else
led7<= "11111111";
  end if;
end process;

end Behavioral;