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ATI XilleonTM 220 TV haute définition de données
Chapitre 1: Introduction
1.1
A propos de ce manuel .............................................. .................................................. ...................1-1
ATI Component 1.2 Numéro de pièce Legend ............................................ ........................................1-1
1.3 Conventions et Notations .............................................. .................................................. .....1-3
1.3.1 Pin / Signal Names ........................................... .................................................. ........1-3
1.3.2 Types Pin ............................................. .................................................. ...................1-3
1.3.3 Représentation numérique ............................................. ..............................................1-4
1.3.4 Acronymes .............................................. .................................................. .................1-4
Chapitre 2: Device Architecture
2.1
Vue d'ensemble ................................................ .................................................. ..............................2-1
2.2 Schéma de ............................................... .................................................. .......................2-2
2.2.1 Multimedia Subsystem ............................................. ................................................2-3
2.2.2 processeur MIPS ............................................. .................................................. .........2-3
2.2.3 Interface PCI ............................................. .................................................. ..............2-3
2.2.4 périphériques PCI ............................................. .................................................. ..........2-4
2.2.5 Autres périphériques ............................................. .................................................. .......2-4
2.2.6 Memory Controller ............................................. .................................................. ....2-4
2.3 Modes de fonctionnement du dispositif de .............................................. .................................................. ........2-5
2.4 Adresse Carte ............................................... .................................................. ..........................2-7
2.4.1 programmable Adresse Ouverture ............................................ ................................2-7
2.4.2 Exemple de carte postale pour un système ......................................... ...............................2-8
2.5 Reset ................................................ .................................................. ...................................2-13
Boot Sequence 2.6 ............................................... .................................................. ......................2-14
2.6.1 Séquence de démarrage SOLO Configurations .......................................... ....................2-14
2.6.2 Séquence de démarrage et PEER PEERPlus Configurations ......................................2-14
2.7 Interruption ................................................ .................................................. ..............................2-16
2.7.1 Introduction .............................................. .................................................. ............2-16
2.7.2 Block Level Interrupt Structure ........................................... ...................................2-17
Chip Level Interrupt 2.7.3 Structure ........................................... .....................................2-20
2.7.4 Structure MIPS Interrupt ............................................ ............................................2-27
2.7.5 Xilleon 220 Interrupt Service Flow .......................................... ..............................2-29
2.7.6 Résumé de l'interruption des groupes ........................................... .....................................2-32
Chapitre 3: Multimedia Subsystem
3.1 Introduction ................................................ .................................................. ...........................3-1
3.2 Le Stream Interface .............................................. .................................................. ...............3-2
3.2.1 Introduction .............................................. .................................................. ...............3-2
3.2.2 Caractéristiques .............................................. .................................................. .....................3-2
3.2.3 Théorie de l'opération ............................................ .................................................. ...3-3
3.2.4 Interfaces externes ............................................. .................................................. ...3-14
3.2.5 Performance .............................................. .................................................. ............3-15
3.3 Transport Demultiplexer ............................................... .................................................. ......3-16
3.3.1 Introduction .............................................. .................................................. .............3-16
3.3.2 Description fonctionnelle ............................................. ...............................................3-21
3.3.3 Support Microcode ............................................. .................................................. ..3-28
3.3.4 Filtrage sur les transports Header Fields .......................................... ............................3-33
3.3.5 Extraction de données de contrôle Flag - Ajout de la fonctionnalité (EXTR_PID) ............3-34
Stream 3.3.6 Syntaxe de suivi et de la statistique (CHK_PID )....................................... ....3-35
3.3.7 Backbone Transport Bus (TBB )......................................... ....................................3-36
3.3.8 General Purpose IO Pins ........................................... ..............................................3-39
3.3.9 Debugging .............................................. .................................................. ...............3-39
3.3.10 Interfaces externes ............................................. .................................................. ...3-39
3.3.11 Enregistrement et Time Stamping ........................................... ....................................3-41
3.3.12 Time Shifting et Bit Rate Recovery ......................................... ............................3-42
Trick 3.3.13 Mode de lecture de code de suivi et de l'image (PCM )..................................3-42
3.3.14 Picture-In-Picture (PIP) ....................................... .................................................. .3-43
3.3.15 Packet Substitution (SUBS_PID) .......................................... .................................3-43
Clock Recovery 3.3.16 ............................................. .................................................. .......3-43
3.3.17 de synchronisation audio / vidéo ........................................... .....................................3-44
3.3.18 Interrupts .............................................. .................................................. .................3-45
3.3.19 Horloge de vitesse et de latence ........................................... ..........................................3-45
3.4 Conditional Access Module .............................................. .................................................. ..3-46
3.4.1 System-Level Description ........................................... ...........................................3-46
3.4.2 Module CA Caractéristiques ............................................ .................................................. .3-46
3.4.3 Description de premier niveau ........................................... .................................................3-47
3.4.4 Avant de décryptage Clés de stockage dans le tableau CW ...................................... .....3-47
3.5 Smart Card Interfaces .............................................. .................................................. ............3-49
3.5.1 Introduction .............................................. .................................................. .............3-49
3.5.2 Liste de ............................................. .................................................. ..............3-49
3.5.3 Description fonctionnelle ............................................. ...............................................3-50
3.5.4 Interfaces externes Chip ............................................ .............................................3-56
3.5.5 Performance .............................................. .................................................. ............3-57
Décodeur MPEG 3.6 ............................................... .................................................. ....................3-57
3.6.1 Caractéristiques .............................................. .................................................. ...................3-57
3.6.2 Description fonctionnelle ............................................. ...............................................3-58
3.6.3 Adaptive Compression Decode Filter Support .......................................... .............3-63
3.6.4 Performance .............................................. .................................................. ............3-66
3.6.5 Error Recovery Concealment ............................................ .....................................3-66
3.7 Le Sous-système audio .............................................. .................................................. ...........3-67
3.7.1 Introduction .............................................. .................................................. ............3-67
3.7.2 Audio Feature List ............................................ .................................................. ....3-67
3.7.3 Décodeur audio Schéma ........................................... ...................................3-68
3.7.4 Flux de données audio Inside Xilleon 220 ......................................... .............................3-69
3.7.5 Mixage Audio ............................................. .................................................. ..........3-71
3.7.6 Détection d'erreur de récupération / Concealment .......................................... .......................3-72
3.7.7 Interface I2S ............................................. .................................................. ............3-73
3.7.8 AC-Link Interface ........................................... .................................................. .....3-77
3.8 Sous-système d'affichage ............................................... .................................................. ...............3-78
3.8.1 Introduction .............................................. .................................................. ............3-78
3.8.2 Caractéristiques .............................................. .................................................. ...................3-78
3.8.3 Schéma de ............................................. .................................................. .........3-79
3.8.4 Flux de données ............................................. .................................................. ................3-80
3.8.5 TV Encodeurs ............................................. .................................................. ............3-81
3.8.6 Théorie de l'opération ............................................ .................................................. .3-88
3.8.7 Interfaces externes ............................................. .................................................. ...3-93
3.8.8 Linéarité, SNR, Jitter, chronométrage, et la couleur Considerations .................................... .3-94
3.8.9 Configuration pour différentes des normes de la radiotélévision .......................................... ......3-94
3.8.10 Mode Tables ............................................. .................................................. ............3-94
2D/3D Moteurs 3.9 ............................................. .................................................. .......................3-96
3.9.1 Caractéristiques 2D ............................................. .................................................. ..............3-96
3.9.2 Moteur 2D Description fonctionnelle ........................................... ..............................3-96
3.9.3 Caractéristiques 3D ............................................. .................................................. ..............3-96
3.9.4 Description fonctionnelle moteur 3D ........................................... ..............................3-97
Chapitre 4: processeur MIPS
4.1 Aperçu ................................................ .................................................. ..............................4-1
4.2 Fonctionnalités ............................................... .................................................. ...........................4-1
4.3 Embedded Xilleon 220 MIPS fonctionnalité ............................................ ...............................4-3
4.3.1 Xilleon 220 MIPS Embedded Haut Niveau Schéma ........................................ ..........4-3
4.3.2 Théorie de l'opération ............................................ .................................................. ...4-4
Chapitre 5: Interface PCI
5.1 PCI Controller (Host Bridge )........................................... .................................................. .....5-1
5.1.1 Aperçu .............................................. .................................................. ..................5-1
5.1.2 Liste de ............................................. .................................................. ................5-2
5.2 Functional Description ............................................... .................................................. ...........5-3
5.2.1 Schéma de ............................................. .................................................. ...........5-3
5.2.2 Théorie de l'opération ............................................ .................................................. ...5-4
5.3 Interfaces externes Chip .............................................. .................................................. ..........5-8
5.3.1 Interface de bus PCI ............................................ .................................................. ........5-8
Chapitre 6: périphériques PCI
6.1 Introduction ................................................ .................................................. ...........................6-1
6.2 Enhanced Integrated Drive Electronics (EIDE) Controller ......................................... ............6-2
6.2.1 Liste de ............................................. .................................................. ................6-2
6.2.2 Description fonctionnelle ............................................. .................................................6-3
6.3 Universal Serial Bus (USB) Controller .......................................... .......................................6-10
6.3.1 Liste de ............................................. .................................................. ..............6-10
6.3.2 Description fonctionnelle ............................................. ................................................ 6 -- 11
6.3.3 Performance .............................................. .................................................. ............6-16
6.4 Low-Pin Count (LPC) Interface Controller ........................................ ..................................6-17
6.4.1 Aperçu .............................................. .................................................. .................6-17
6.4.2 Liste de ............................................. .................................................. ..............6-17
6.4.3 Description fonctionnelle ............................................. ...............................................6-18
6.5 AC-Link Interface ............................................. .................................................. ..................6-21
6.5.1 Aperçu .............................................. .................................................. .................6-21
6.5.2 Liste de ............................................. .................................................. ..............6-22
6.5.3 Description fonctionnelle ............................................. ...............................................6-22
6.5.4 Interfaces externes Chip ............................................ .............................................6-28
6.5.5 Performance .............................................. .................................................. ............6-29
Chapitre 7: Autres périphériques
7.1 Introduction ................................................ .................................................. ...........................7-1
7.2 Objectif général de minuteries et Real-Time Clock ......................................... ..............................7-3
7,3 FlexBus (Flexible Peripheral Bus) ........................................... ...............................................7-7
7.3.1 Aperçu .............................................. .................................................. ...................7-7
7.3.2 Liste de ............................................. .................................................. ................7-7
Bus 7.3.3 Aperçu ............................................. .................................................. ............7-8
7.3.4 Description fonctionnelle ............................................. ...............................................7-10
7.3.5 Programming Considerations ............................................. ....................................7-13
7.3.6 Interfaces externes Chip ............................................ .............................................7-17
7.3.7 Performance .............................................. .................................................. ............7-21
7.4 Universal Asynchronous Receiver / Transmitters (UART )......................................... ..........7-22
7.4.1 Aperçu .............................................. .................................................. .................7-22
7.4.2 Liste de ............................................. .................................................. ..............7-22
7.4.3 Description fonctionnelle ............................................. ...............................................7-23
7.4.4 Interfaces externes Chip ............................................ .............................................7-27
7.4.5 Performance .............................................. .................................................. ............7-27
7.5 Universal Infrared Receiver / Transmitter (UIRT) ......................................... ........................7-28
7.5.1 Aperçu .............................................. .................................................. ................7-28
7.5.2 Liste de ............................................. .................................................. ..............7-28
7.5.3 Description fonctionnelle ............................................. ..............................................7-29
7.5.4 Interfaces externes Chip ............................................ .............................................7-37
7.5.5 Contexte IR ............................................. .................................................. .........7-38
7,6 unité périphérique DMA .............................................. .................................................. ............7-43
7.6.1 Aperçu .............................................. .................................................. ................7-43
7.6.2 Liste de ............................................. .................................................. ..............7-43
7.6.3 Description fonctionnelle ............................................. ..............................................7-44
7.6.4 Interfaces externes Chip ............................................ .............................................7-50
7.7 Matériel de contrôle I2C Serial Ports ............................................ ......................................7-51
7.7.1 Aperçu .............................................. .................................................. ................7-51
7.7.2 Liste de ............................................. .................................................. ..............7-51
7.7.3 Functional Descriptions ............................................. .............................................7-51
7.7.4 Schéma de I2C Master .......................................... ......................................7-53
7.7.5 Théorie de l'opération ............................................ .................................................. .7-53
7.7.6 Flux de données ............................................. .................................................. ................7-57
VIP 7.8 Host Port .............................................. .................................................. ........................7-57
7.8.1 Aperçu .............................................. .................................................. ................7-57
7.8.2 Liste de ............................................. .................................................. ..............7-57
7.8.3 Functional Descriptions ............................................. .............................................7-58
7.8.4 VIP Host Controller Schéma .......................................... .....................7-59
7.8.5 Théorie de l'opération ............................................ .................................................. .7-59
7.8.6 Flux de données ............................................. .................................................. ................7-63
Chapitre 8: Memory Controller
8.1 Introduction ................................................ .................................................. ..........................8-1
8.2 Feature List ............................................... .................................................. ............................8-1
8.3 External Memory Support .............................................. .................................................. .......8-2
8.4 Functional Description ............................................... .................................................. ...........8-4
8.4.1 Schéma de ............................................. .................................................. ...........8-4
8.4.2 Théorie de l'opération ............................................ .................................................. ...8-5
8.4.3 Performance Limitations et restrictions ........................................... ..................8-13
8.4.4 PC Board Design Considerations ........................................... ................................8-14
Chapitre 9: Pinout Descriptions et Strap
9.1 Sommaire Pin ............................................... .................................................. .........................9-1
9,2 Xilleon 220 Pin Assignment Haut-View .......................................... ........................................9-2
9.3 Signal Liste ............................................... .................................................. ..............................9-4
9.3.1 Interface PCI ............................................. .................................................. ..............9-4
9.3.2 Smart Card Interface ............................................ .................................................. ...9-4
9.3.3 Mémoire (Dual Channel) Interface ......................................... ...................................9-6
9.3.4 Transport Stream Interface ............................................ ...........................................9-7
9.3.5 PLL
et XTAL ............................................ .................................................. ............9-8
9.3.6 CRTC Interface ............................................. .................................................. ..........9-9
9.3.7 Enseignement primaire et secondaire DAC affichage .......................................... ............................9-9
9.3.8 DVI Out Interface ............................................ .................................................. ...... 9.11
9.3.9 UIT-656 In / Out Interface ........................................ ................................................. 9 -11
9.3.10 Interface SPDIF ............................................. .................................................. .......9-12
9.3.11 Interface I2S ............................................. .................................................. .............9-13
9.3.12 Interface I2C ............................................. .................................................. ............9-13
9.3.13 AC-Link Interface ........................................... .................................................. ......9-14
9.3.14 Timers Interface Port ............................................ ..................................................9-14
9.3.15 General Purpose Interface BUS ........................................... ...................................9-15
9.3.16 VIP Interface ............................................. .................................................. ............9-17
9.3.17 Test Pin ............................................. .................................................. ....................9-17
9.3.18 Serial Port Interface ............................................ .................................................. ..9-17
9.3.19 Interface LPC ............................................. .................................................. ...........9-18
9.3.20 Serial Port A et le LPC Multiplexing ......................................... .............................9-18
9.3.21 PCI Bus Multiplexing ............................................ .................................................9-19
9.3.22 Interface FlexBus ............................................. .................................................. .....9-20
9.3.23 Interface USB ............................................. .................................................. ..........9-21
9.3.24 Serial Interface IEEE 1394 ........................................... ..........................................9-22
9.3.25 Sur la bande Interface ........................................... ..................................................9-22
9.3.26 Infrarouge Réception / Transmission Interface .......................................... .............................9-22
9.3.27 Interface IDE ............................................. .................................................. ...........9-23
9.3.28 Interface EJTAG ............................................. .................................................. ......9-23
9.3.29 Power and Ground Pins ........................................... ...............................................9-23
9.4 Configuration / Straps .............................................. .................................................. .............9-24
9.5 par défaut interne Pull-up/down Resistor Mapping ........................................ .........................9-26
Chapitre 10: Caractéristiques physiques et électriques
10.1 DC / AC Caractéristiques ............................................. .................................................. .........10-1
10.1.1 DC Caractéristiques ............................................. .................................................. ...10-1
10.1.2 AC Caractéristiques: ............................................ .................................................. ...10-1
10,2 Dissipation de puissance ............................................... .................................................. ..............10-2
10.2.1 Conditions d'essai ............................................. .................................................. ........10-2
10.2.2 Test # 1 -
Le double affichage SDTV MPEG seulement ...................................... ..................10-3
10.2.3 Test # 2 - Dual HD / HD avec moteur graphique 2D/3D Clk Sur ................10-4
10.3 Power Up séquences .............................................. .................................................. ............10-5
10,4 Dimensions physiques ............................................... .................................................. ..........10-7
10,5 Brasage / Reflow Profil ............................................. .................................................. ...10-9
Chapitre 11: Calendrier Spécifications
11,1 PCI Bus Timing .............................................. .................................................. ................... 11-2
11.1.1 Lire Single Cycle Timing ........................................... ............................................ 11-3
11.1.2 Ecrire Single Cycle Timing ........................................... ........................................... 11-4
11.1.3 Burst Lire Cycle Timing ........................................... ............................................. 11-5
11.1.4 Burst Write Cycle Time ........................................... ................................................ 11 -- 6
11.1.5 PCI Bus Master Operation ........................................... ............................................ 11-7
11.1.6 Target Abort Termination ............................................ ............................................ 11-8
11.1.7 Objectif Déconnectez avec ou sans données ......................................... ........................ 11-9
11.1.8 Master Abort Termination ............................................ ......................................... 11-10
11.1.9 Target Abort Termination ............................................ .......................................... 11-10
11.1.10 SERRb Timing ............................................. .................................................. .......11-11
11.1.11 PERRb Timing ............................................. .................................................. .......11-11
11,2 Smart Card Timing .............................................. .................................................. 11-13 .............
11,3 Memory Timing ............................................... .................................................. ................ 11-16
11.3.1 Single Data Rate SDRAM / SGRAM ......................................... ............................ 11-16
11.3.2 Double Data Rate SDRAM / SGRAM ......................................... ........................... 11-16
11.3.3 Programmation Timing valeurs ............................................ .................................... 11-1811.3.4 Single Data Rate (SDR) SGRAM/SDRAM Timing Diagrams.............................11-20
11.3.5 Double Data Rate (DDR) SGRAM Timing Diagrams..........................................11-22
11.3.6 Input/Output Timing..............................................................................................11-25
11.4 Transport Stream Interface Timing....................................................................................11-29
11.4.1 Input Stream (A and B) and Out of Band..............................................................11-29
11.4.2 Output Stream C (Normal Mode)..........................................................................11-30
11.4.3 NRSS Timing ........................................................................................................11-31
11.5 DVI Out Timing.................................................................................................................11-32
11.6 ITU-656 Timing.................................................................................................................11-33
11.6.1 ITU-656 In.............................................................................................................11-33
11.6.2 ITU-656 Out ..........................................................................................................11-34
11.7 SPDIF Timing ....................................................................................................................11-35
11.8 I2S Bus Timing ..................................................................................................................11-36
11.8.1 I2S Transmitter Timing .........................................................................................11-36
11.8.2 I2S Receiver Timing..............................................................................................11-38
11.9 I2C Timing .........................................................................................................................11-39
11.9.1 Write Cycle............................................................................................................11-39
11.9.2 Read Cycle.............................................................................................................11-40
11.10 AC-Link Timing ..............................................................................................................11-41
11.11 Timer Port Timing............................................................................................................11-43
11.12 VIP Host Timing ..............................................................................................................11-44
11.13 UART (Serial Port) Timing..............................................................................................11-45
11.14 LPC Timing......................................................................................................................11-46
11.14.1 Memory Read Cycle Timing .................................................................................11-46
11.14.2 Memory Write Cycle Timing ................................................................................11-47
11.14.3 IO Read Cycle Timing...........................................................................................11-48
11.14.4 IO Write Cycle Timing..........................................................................................11-48
11.15 FlexBus Timing................................................................................................................11-50
11.15.1 Bus Request/Grant Protocol ..................................................................................11-51
11.15.2 Address Bus Connection........................................................................................11-52
11.15.3 Example Connection to an 8-bit Flash ROM Device ............................................11-54
11.15.4 Example Connection to a DOCSIS Media Access Control (MAC) Device..........11-57
11.16 USB Timing .....................................................................................................................11-60
11.17 IEEE 1394 LINK Layer Chip Timing..............................................................................11-61
11.18 UIRT Timing....................................................................................................................11-62
11.19 IDE Timing ......................................................................................................................11-63
11.19.1 PIO Mode Timing..................................................................................................11-63
11.19.2 DMA Mode Timing...............................................................................................11-64
11.19.3 Register Transfer to/from Device ..........................................................................11-65
11.19.4 PIO Data Transfer to/from Device ........................................................................11-66
11.19.5 Multiword DMA Data Transfer.............................................................................11-67
11.19.6 Initiating an Ultra DMA Data-in Burst..................................................................11-68
11.19.7 Sustained Ultra DMA Data-in Burst......................................................................11-69
11.20 EJTAG Port Timing .........................................................................................................11-70
Chapter 12: EXOR Tree
12.1 Brief Description of an EXOR Tree....................................................................................
12-112.2 Description of the EXOR Tree for Xilleon 220 ..................................................................
12-112.2.1 Connections ............................................................................................................
12-212.2.2 EXOR Tree Activation ...........................................................................................
12-212.2.3 Unused Pins ............................................................................................................
12-2Appendix A: Pinout Listing
Pins Sorted by Signal Name .........................................................................................................
A-2Pins Sorted by Ball Reference ....................................................................................................
A-10Appendix B: Revision HistoryDésolé, mais vous avez besoin de login pour afficher cette pièce jointe
Chapitre 1: Introduction
1.1
A propos de ce manuel .............................................. .................................................. ...................1-1
ATI Component 1.2 Numéro de pièce Legend ............................................ ........................................1-1
1.3 Conventions et Notations .............................................. .................................................. .....1-3
1.3.1 Pin / Signal Names ........................................... .................................................. ........1-3
1.3.2 Types Pin ............................................. .................................................. ...................1-3
1.3.3 Représentation numérique ............................................. ..............................................1-4
1.3.4 Acronymes .............................................. .................................................. .................1-4
Chapitre 2: Device Architecture
2.1
Vue d'ensemble ................................................ .................................................. ..............................2-1
2.2 Schéma de ............................................... .................................................. .......................2-2
2.2.1 Multimedia Subsystem ............................................. ................................................2-3
2.2.2 processeur MIPS ............................................. .................................................. .........2-3
2.2.3 Interface PCI ............................................. .................................................. ..............2-3
2.2.4 périphériques PCI ............................................. .................................................. ..........2-4
2.2.5 Autres périphériques ............................................. .................................................. .......2-4
2.2.6 Memory Controller ............................................. .................................................. ....2-4
2.3 Modes de fonctionnement du dispositif de .............................................. .................................................. ........2-5
2.4 Adresse Carte ............................................... .................................................. ..........................2-7
2.4.1 programmable Adresse Ouverture ............................................ ................................2-7
2.4.2 Exemple de carte postale pour un système ......................................... ...............................2-8
2.5 Reset ................................................ .................................................. ...................................2-13
Boot Sequence 2.6 ............................................... .................................................. ......................2-14
2.6.1 Séquence de démarrage SOLO Configurations .......................................... ....................2-14
2.6.2 Séquence de démarrage et PEER PEERPlus Configurations ......................................2-14
2.7 Interruption ................................................ .................................................. ..............................2-16
2.7.1 Introduction .............................................. .................................................. ............2-16
2.7.2 Block Level Interrupt Structure ........................................... ...................................2-17
Chip Level Interrupt 2.7.3 Structure ........................................... .....................................2-20
2.7.4 Structure MIPS Interrupt ............................................ ............................................2-27
2.7.5 Xilleon 220 Interrupt Service Flow .......................................... ..............................2-29
2.7.6 Résumé de l'interruption des groupes ........................................... .....................................2-32
Chapitre 3: Multimedia Subsystem
3.1 Introduction ................................................ .................................................. ...........................3-1
3.2 Le Stream Interface .............................................. .................................................. ...............3-2
3.2.1 Introduction .............................................. .................................................. ...............3-2
3.2.2 Caractéristiques .............................................. .................................................. .....................3-2
3.2.3 Théorie de l'opération ............................................ .................................................. ...3-3
3.2.4 Interfaces externes ............................................. .................................................. ...3-14
3.2.5 Performance .............................................. .................................................. ............3-15
3.3 Transport Demultiplexer ............................................... .................................................. ......3-16
3.3.1 Introduction .............................................. .................................................. .............3-16
3.3.2 Description fonctionnelle ............................................. ...............................................3-21
3.3.3 Support Microcode ............................................. .................................................. ..3-28
3.3.4 Filtrage sur les transports Header Fields .......................................... ............................3-33
3.3.5 Extraction de données de contrôle Flag - Ajout de la fonctionnalité (EXTR_PID) ............3-34
Stream 3.3.6 Syntaxe de suivi et de la statistique (CHK_PID )....................................... ....3-35
3.3.7 Backbone Transport Bus (TBB )......................................... ....................................3-36
3.3.8 General Purpose IO Pins ........................................... ..............................................3-39
3.3.9 Debugging .............................................. .................................................. ...............3-39
3.3.10 Interfaces externes ............................................. .................................................. ...3-39
3.3.11 Enregistrement et Time Stamping ........................................... ....................................3-41
3.3.12 Time Shifting et Bit Rate Recovery ......................................... ............................3-42
Trick 3.3.13 Mode de lecture de code de suivi et de l'image (PCM )..................................3-42
3.3.14 Picture-In-Picture (PIP) ....................................... .................................................. .3-43
3.3.15 Packet Substitution (SUBS_PID) .......................................... .................................3-43
Clock Recovery 3.3.16 ............................................. .................................................. .......3-43
3.3.17 de synchronisation audio / vidéo ........................................... .....................................3-44
3.3.18 Interrupts .............................................. .................................................. .................3-45
3.3.19 Horloge de vitesse et de latence ........................................... ..........................................3-45
3.4 Conditional Access Module .............................................. .................................................. ..3-46
3.4.1 System-Level Description ........................................... ...........................................3-46
3.4.2 Module CA Caractéristiques ............................................ .................................................. .3-46
3.4.3 Description de premier niveau ........................................... .................................................3-47
3.4.4 Avant de décryptage Clés de stockage dans le tableau CW ...................................... .....3-47
3.5 Smart Card Interfaces .............................................. .................................................. ............3-49
3.5.1 Introduction .............................................. .................................................. .............3-49
3.5.2 Liste de ............................................. .................................................. ..............3-49
3.5.3 Description fonctionnelle ............................................. ...............................................3-50
3.5.4 Interfaces externes Chip ............................................ .............................................3-56
3.5.5 Performance .............................................. .................................................. ............3-57
Décodeur MPEG 3.6 ............................................... .................................................. ....................3-57
3.6.1 Caractéristiques .............................................. .................................................. ...................3-57
3.6.2 Description fonctionnelle ............................................. ...............................................3-58
3.6.3 Adaptive Compression Decode Filter Support .......................................... .............3-63
3.6.4 Performance .............................................. .................................................. ............3-66
3.6.5 Error Recovery Concealment ............................................ .....................................3-66
3.7 Le Sous-système audio .............................................. .................................................. ...........3-67
3.7.1 Introduction .............................................. .................................................. ............3-67
3.7.2 Audio Feature List ............................................ .................................................. ....3-67
3.7.3 Décodeur audio Schéma ........................................... ...................................3-68
3.7.4 Flux de données audio Inside Xilleon 220 ......................................... .............................3-69
3.7.5 Mixage Audio ............................................. .................................................. ..........3-71
3.7.6 Détection d'erreur de récupération / Concealment .......................................... .......................3-72
3.7.7 Interface I2S ............................................. .................................................. ............3-73
3.7.8 AC-Link Interface ........................................... .................................................. .....3-77
3.8 Sous-système d'affichage ............................................... .................................................. ...............3-78
3.8.1 Introduction .............................................. .................................................. ............3-78
3.8.2 Caractéristiques .............................................. .................................................. ...................3-78
3.8.3 Schéma de ............................................. .................................................. .........3-79
3.8.4 Flux de données ............................................. .................................................. ................3-80
3.8.5 TV Encodeurs ............................................. .................................................. ............3-81
3.8.6 Théorie de l'opération ............................................ .................................................. .3-88
3.8.7 Interfaces externes ............................................. .................................................. ...3-93
3.8.8 Linéarité, SNR, Jitter, chronométrage, et la couleur Considerations .................................... .3-94
3.8.9 Configuration pour différentes des normes de la radiotélévision .......................................... ......3-94
3.8.10 Mode Tables ............................................. .................................................. ............3-94
2D/3D Moteurs 3.9 ............................................. .................................................. .......................3-96
3.9.1 Caractéristiques 2D ............................................. .................................................. ..............3-96
3.9.2 Moteur 2D Description fonctionnelle ........................................... ..............................3-96
3.9.3 Caractéristiques 3D ............................................. .................................................. ..............3-96
3.9.4 Description fonctionnelle moteur 3D ........................................... ..............................3-97
Chapitre 4: processeur MIPS
4.1 Aperçu ................................................ .................................................. ..............................4-1
4.2 Fonctionnalités ............................................... .................................................. ...........................4-1
4.3 Embedded Xilleon 220 MIPS fonctionnalité ............................................ ...............................4-3
4.3.1 Xilleon 220 MIPS Embedded Haut Niveau Schéma ........................................ ..........4-3
4.3.2 Théorie de l'opération ............................................ .................................................. ...4-4
Chapitre 5: Interface PCI
5.1 PCI Controller (Host Bridge )........................................... .................................................. .....5-1
5.1.1 Aperçu .............................................. .................................................. ..................5-1
5.1.2 Liste de ............................................. .................................................. ................5-2
5.2 Functional Description ............................................... .................................................. ...........5-3
5.2.1 Schéma de ............................................. .................................................. ...........5-3
5.2.2 Théorie de l'opération ............................................ .................................................. ...5-4
5.3 Interfaces externes Chip .............................................. .................................................. ..........5-8
5.3.1 Interface de bus PCI ............................................ .................................................. ........5-8
Chapitre 6: périphériques PCI
6.1 Introduction ................................................ .................................................. ...........................6-1
6.2 Enhanced Integrated Drive Electronics (EIDE) Controller ......................................... ............6-2
6.2.1 Liste de ............................................. .................................................. ................6-2
6.2.2 Description fonctionnelle ............................................. .................................................6-3
6.3 Universal Serial Bus (USB) Controller .......................................... .......................................6-10
6.3.1 Liste de ............................................. .................................................. ..............6-10
6.3.2 Description fonctionnelle ............................................. ................................................ 6 -- 11
6.3.3 Performance .............................................. .................................................. ............6-16
6.4 Low-Pin Count (LPC) Interface Controller ........................................ ..................................6-17
6.4.1 Aperçu .............................................. .................................................. .................6-17
6.4.2 Liste de ............................................. .................................................. ..............6-17
6.4.3 Description fonctionnelle ............................................. ...............................................6-18
6.5 AC-Link Interface ............................................. .................................................. ..................6-21
6.5.1 Aperçu .............................................. .................................................. .................6-21
6.5.2 Liste de ............................................. .................................................. ..............6-22
6.5.3 Description fonctionnelle ............................................. ...............................................6-22
6.5.4 Interfaces externes Chip ............................................ .............................................6-28
6.5.5 Performance .............................................. .................................................. ............6-29
Chapitre 7: Autres périphériques
7.1 Introduction ................................................ .................................................. ...........................7-1
7.2 Objectif général de minuteries et Real-Time Clock ......................................... ..............................7-3
7,3 FlexBus (Flexible Peripheral Bus) ........................................... ...............................................7-7
7.3.1 Aperçu .............................................. .................................................. ...................7-7
7.3.2 Liste de ............................................. .................................................. ................7-7
Bus 7.3.3 Aperçu ............................................. .................................................. ............7-8
7.3.4 Description fonctionnelle ............................................. ...............................................7-10
7.3.5 Programming Considerations ............................................. ....................................7-13
7.3.6 Interfaces externes Chip ............................................ .............................................7-17
7.3.7 Performance .............................................. .................................................. ............7-21
7.4 Universal Asynchronous Receiver / Transmitters (UART )......................................... ..........7-22
7.4.1 Aperçu .............................................. .................................................. .................7-22
7.4.2 Liste de ............................................. .................................................. ..............7-22
7.4.3 Description fonctionnelle ............................................. ...............................................7-23
7.4.4 Interfaces externes Chip ............................................ .............................................7-27
7.4.5 Performance .............................................. .................................................. ............7-27
7.5 Universal Infrared Receiver / Transmitter (UIRT) ......................................... ........................7-28
7.5.1 Aperçu .............................................. .................................................. ................7-28
7.5.2 Liste de ............................................. .................................................. ..............7-28
7.5.3 Description fonctionnelle ............................................. ..............................................7-29
7.5.4 Interfaces externes Chip ............................................ .............................................7-37
7.5.5 Contexte IR ............................................. .................................................. .........7-38
7,6 unité périphérique DMA .............................................. .................................................. ............7-43
7.6.1 Aperçu .............................................. .................................................. ................7-43
7.6.2 Liste de ............................................. .................................................. ..............7-43
7.6.3 Description fonctionnelle ............................................. ..............................................7-44
7.6.4 Interfaces externes Chip ............................................ .............................................7-50
7.7 Matériel de contrôle I2C Serial Ports ............................................ ......................................7-51
7.7.1 Aperçu .............................................. .................................................. ................7-51
7.7.2 Liste de ............................................. .................................................. ..............7-51
7.7.3 Functional Descriptions ............................................. .............................................7-51
7.7.4 Schéma de I2C Master .......................................... ......................................7-53
7.7.5 Théorie de l'opération ............................................ .................................................. .7-53
7.7.6 Flux de données ............................................. .................................................. ................7-57
VIP 7.8 Host Port .............................................. .................................................. ........................7-57
7.8.1 Aperçu .............................................. .................................................. ................7-57
7.8.2 Liste de ............................................. .................................................. ..............7-57
7.8.3 Functional Descriptions ............................................. .............................................7-58
7.8.4 VIP Host Controller Schéma .......................................... .....................7-59
7.8.5 Théorie de l'opération ............................................ .................................................. .7-59
7.8.6 Flux de données ............................................. .................................................. ................7-63
Chapitre 8: Memory Controller
8.1 Introduction ................................................ .................................................. ..........................8-1
8.2 Feature List ............................................... .................................................. ............................8-1
8.3 External Memory Support .............................................. .................................................. .......8-2
8.4 Functional Description ............................................... .................................................. ...........8-4
8.4.1 Schéma de ............................................. .................................................. ...........8-4
8.4.2 Théorie de l'opération ............................................ .................................................. ...8-5
8.4.3 Performance Limitations et restrictions ........................................... ..................8-13
8.4.4 PC Board Design Considerations ........................................... ................................8-14
Chapitre 9: Pinout Descriptions et Strap
9.1 Sommaire Pin ............................................... .................................................. .........................9-1
9,2 Xilleon 220 Pin Assignment Haut-View .......................................... ........................................9-2
9.3 Signal Liste ............................................... .................................................. ..............................9-4
9.3.1 Interface PCI ............................................. .................................................. ..............9-4
9.3.2 Smart Card Interface ............................................ .................................................. ...9-4
9.3.3 Mémoire (Dual Channel) Interface ......................................... ...................................9-6
9.3.4 Transport Stream Interface ............................................ ...........................................9-7
9.3.5 PLL
et XTAL ............................................ .................................................. ............9-8
9.3.6 CRTC Interface ............................................. .................................................. ..........9-9
9.3.7 Enseignement primaire et secondaire DAC affichage .......................................... ............................9-9
9.3.8 DVI Out Interface ............................................ .................................................. ...... 9.11
9.3.9 UIT-656 In / Out Interface ........................................ ................................................. 9 -11
9.3.10 Interface SPDIF ............................................. .................................................. .......9-12
9.3.11 Interface I2S ............................................. .................................................. .............9-13
9.3.12 Interface I2C ............................................. .................................................. ............9-13
9.3.13 AC-Link Interface ........................................... .................................................. ......9-14
9.3.14 Timers Interface Port ............................................ ..................................................9-14
9.3.15 General Purpose Interface BUS ........................................... ...................................9-15
9.3.16 VIP Interface ............................................. .................................................. ............9-17
9.3.17 Test Pin ............................................. .................................................. ....................9-17
9.3.18 Serial Port Interface ............................................ .................................................. ..9-17
9.3.19 Interface LPC ............................................. .................................................. ...........9-18
9.3.20 Serial Port A et le LPC Multiplexing ......................................... .............................9-18
9.3.21 PCI Bus Multiplexing ............................................ .................................................9-19
9.3.22 Interface FlexBus ............................................. .................................................. .....9-20
9.3.23 Interface USB ............................................. .................................................. ..........9-21
9.3.24 Serial Interface IEEE 1394 ........................................... ..........................................9-22
9.3.25 Sur la bande Interface ........................................... ..................................................9-22
9.3.26 Infrarouge Réception / Transmission Interface .......................................... .............................9-22
9.3.27 Interface IDE ............................................. .................................................. ...........9-23
9.3.28 Interface EJTAG ............................................. .................................................. ......9-23
9.3.29 Power and Ground Pins ........................................... ...............................................9-23
9.4 Configuration / Straps .............................................. .................................................. .............9-24
9.5 par défaut interne Pull-up/down Resistor Mapping ........................................ .........................9-26
Chapitre 10: Caractéristiques physiques et électriques
10.1 DC / AC Caractéristiques ............................................. .................................................. .........10-1
10.1.1 DC Caractéristiques ............................................. .................................................. ...10-1
10.1.2 AC Caractéristiques: ............................................ .................................................. ...10-1
10,2 Dissipation de puissance ............................................... .................................................. ..............10-2
10.2.1 Conditions d'essai ............................................. .................................................. ........10-2
10.2.2 Test # 1 -
Le double affichage SDTV MPEG seulement ...................................... ..................10-3
10.2.3 Test # 2 - Dual HD / HD avec moteur graphique 2D/3D Clk Sur ................10-4
10.3 Power Up séquences .............................................. .................................................. ............10-5
10,4 Dimensions physiques ............................................... .................................................. ..........10-7
10,5 Brasage / Reflow Profil ............................................. .................................................. ...10-9
Chapitre 11: Calendrier Spécifications
11,1 PCI Bus Timing .............................................. .................................................. ................... 11-2
11.1.1 Lire Single Cycle Timing ........................................... ............................................ 11-3
11.1.2 Ecrire Single Cycle Timing ........................................... ........................................... 11-4
11.1.3 Burst Lire Cycle Timing ........................................... ............................................. 11-5
11.1.4 Burst Write Cycle Time ........................................... ................................................ 11 -- 6
11.1.5 PCI Bus Master Operation ........................................... ............................................ 11-7
11.1.6 Target Abort Termination ............................................ ............................................ 11-8
11.1.7 Objectif Déconnectez avec ou sans données ......................................... ........................ 11-9
11.1.8 Master Abort Termination ............................................ ......................................... 11-10
11.1.9 Target Abort Termination ............................................ .......................................... 11-10
11.1.10 SERRb Timing ............................................. .................................................. .......11-11
11.1.11 PERRb Timing ............................................. .................................................. .......11-11
11,2 Smart Card Timing .............................................. .................................................. 11-13 .............
11,3 Memory Timing ............................................... .................................................. ................ 11-16
11.3.1 Single Data Rate SDRAM / SGRAM ......................................... ............................ 11-16
11.3.2 Double Data Rate SDRAM / SGRAM ......................................... ........................... 11-16
11.3.3 Programmation Timing valeurs ............................................ .................................... 11-1811.3.4 Single Data Rate (SDR) SGRAM/SDRAM Timing Diagrams.............................11-20
11.3.5 Double Data Rate (DDR) SGRAM Timing Diagrams..........................................11-22
11.3.6 Input/Output Timing..............................................................................................11-25
11.4 Transport Stream Interface Timing....................................................................................11-29
11.4.1 Input Stream (A and B) and Out of Band..............................................................11-29
11.4.2 Output Stream C (Normal Mode)..........................................................................11-30
11.4.3 NRSS Timing ........................................................................................................11-31
11.5 DVI Out Timing.................................................................................................................11-32
11.6 ITU-656 Timing.................................................................................................................11-33
11.6.1 ITU-656 In.............................................................................................................11-33
11.6.2 ITU-656 Out ..........................................................................................................11-34
11.7 SPDIF Timing ....................................................................................................................11-35
11.8 I2S Bus Timing ..................................................................................................................11-36
11.8.1 I2S Transmitter Timing .........................................................................................11-36
11.8.2 I2S Receiver Timing..............................................................................................11-38
11.9 I2C Timing .........................................................................................................................11-39
11.9.1 Write Cycle............................................................................................................11-39
11.9.2 Read Cycle.............................................................................................................11-40
11.10 AC-Link Timing ..............................................................................................................11-41
11.11 Timer Port Timing............................................................................................................11-43
11.12 VIP Host Timing ..............................................................................................................11-44
11.13 UART (Serial Port) Timing..............................................................................................11-45
11.14 LPC Timing......................................................................................................................11-46
11.14.1 Memory Read Cycle Timing .................................................................................11-46
11.14.2 Memory Write Cycle Timing ................................................................................11-47
11.14.3 IO Read Cycle Timing...........................................................................................11-48
11.14.4 IO Write Cycle Timing..........................................................................................11-48
11.15 FlexBus Timing................................................................................................................11-50
11.15.1 Bus Request/Grant Protocol ..................................................................................11-51
11.15.2 Address Bus Connection........................................................................................11-52
11.15.3 Example Connection to an 8-bit Flash ROM Device ............................................11-54
11.15.4 Example Connection to a DOCSIS Media Access Control (MAC) Device..........11-57
11.16 USB Timing .....................................................................................................................11-60
11.17 IEEE 1394 LINK Layer Chip Timing..............................................................................11-61
11.18 UIRT Timing....................................................................................................................11-62
11.19 IDE Timing ......................................................................................................................11-63
11.19.1 PIO Mode Timing..................................................................................................11-63
11.19.2 DMA Mode Timing...............................................................................................11-64
11.19.3 Register Transfer to/from Device ..........................................................................11-65
11.19.4 PIO Data Transfer to/from Device ........................................................................11-66
11.19.5 Multiword DMA Data Transfer.............................................................................11-67
11.19.6 Initiating an Ultra DMA Data-in Burst..................................................................11-68
11.19.7 Sustained Ultra DMA Data-in Burst......................................................................11-69
11.20 EJTAG Port Timing .........................................................................................................11-70
Chapter 12: EXOR Tree
12.1 Brief Description of an EXOR Tree....................................................................................
12-112.2 Description of the EXOR Tree for Xilleon 220 ..................................................................
12-112.2.1 Connections ............................................................................................................
12-212.2.2 EXOR Tree Activation ...........................................................................................
12-212.2.3 Unused Pins ............................................................................................................
12-2Appendix A: Pinout Listing
Pins Sorted by Signal Name .........................................................................................................
A-2Pins Sorted by Ball Reference ....................................................................................................
A-10Appendix B: Revision HistoryDésolé, mais vous avez besoin de login pour afficher cette pièce jointe