K
kuntul
Guest
J'ai un code Verilog ci-dessous.Code:
toujours @ (posedge CLK) commencentForwardA = 0;
ForwardB = 0;/ / EX danger
if (EXMEMRegWrite == 1) commencer
if (EXMEMrd! = 0)
if (EXMEMrd == IDEXrs)
ForwardA = 2'b10;
IDEXTest si (== EXMEMrd IDEXrt & & == 0)
ForwardB = 2'b10;
fin/ Risque MEM /if (MEMWBRegWrite == 1) commencer
if (MEMWBrd! = 0) commencent
if (! (EXMEMRegWrite == 1 & & EXMEMrd! = 0 & & (EXMEMrd == IDEXrs)))
if (MEMWBrd == IDEXrs)
ForwardA = 2'b01;
if (IDEXTest == 0) commencent
if (! (EXMEMRegWrite == 1 & & EXMEMrd! = 0 & & (EXMEMrd == IDEXrt)))
if (MEMWBrd == IDEXrt)
ForwardB = 2'b01;
fin
fin
finfin
toujours @ (posedge CLK) commencentForwardA = 0;
ForwardB = 0;/ / EX danger
if (EXMEMRegWrite == 1) commencer
if (EXMEMrd! = 0)
if (EXMEMrd == IDEXrs)
ForwardA = 2'b10;
IDEXTest si (== EXMEMrd IDEXrt & & == 0)
ForwardB = 2'b10;
fin/ Risque MEM /if (MEMWBRegWrite == 1) commencer
if (MEMWBrd! = 0) commencent
if (! (EXMEMRegWrite == 1 & & EXMEMrd! = 0 & & (EXMEMrd == IDEXrs)))
if (MEMWBrd == IDEXrs)
ForwardA = 2'b01;
if (IDEXTest == 0) commencent
if (! (EXMEMRegWrite == 1 & & EXMEMrd! = 0 & & (EXMEMrd == IDEXrt)))
if (MEMWBrd == IDEXrt)
ForwardB = 2'b01;
fin
fin
finfin